The following forms the core of the virtual clock (VCLK) used by the multi-CPU code generated by the ZMech system. The VCLK allows a low priority background system heartbeat to be generated. The heartbeat allows system wide counters to be maintained on each participating CPU with each counter always being less than 2 apart. When the VCLK is used to bit bang an I2C bus, the I2C bus becomes completely CPU speed independent.One of the advantages of the VCLK as described here, is that CPUs can attach to it or detach from it dynamically at run time. This allows CPUs that have been given a processor intensive task to detach themselves, perform the task then re-attach themselves when they have completed the task (improving the VCLK speed for the rest of the system).
It is required that a CPU Xn signals other CPUs that it is moving from state A to state B then from state B to state A. However Xn cannot move from B to A until all other CPUs have moved from A to B. Said another way, no CPU can move from state A to B until all CPUs are in state A, and no CPU can move from state B to state A until all CPUs are in state B.What we need are the following system states
using 4 open collector signal lines called VCG0, VCG1, VCG2 and VCG3 it is possible to code the 4 states as
STATE DESCRIPTION S0 all CPUs at state A S1 one or more CPUs transitioning from state A to state B S2 all CPUs at state B S3 one or more CPUs transitioning from state B to state A when Xn moves between states it outputs the following
STATE SYMBOL
S0 VCG0 = 1
VCG1 = x
VCG2 = 0
VCG3 = x
S1 VCG0 = x
VCG1 = 1
VCG2 = x
VCG3 = 0
S2 VCG0 = 0
VCG1 = x
VCG2 = 1
VCG3 = x
S3 VCG0 = x
VCG1 = 0
VCG2 = x
VCG3 = 1
STATE
TRANSITION
OUTPUTS
S0 -> S1 VCG0 -> 0
VCG2 -> 1
S1 -> S2 VCG1 -> 0
VCG3 -> 1
S2 -> S3 VCG2 -> 0
VCG0 -> 1
S3 -> S0 VCG3 -> 0
VCG1 -> 1